An example of a conventional CMOS tri-state or 3-state buffer circuit is shown in FIG. 1. Driving circuit 30 has transistors FET1 and FET2 connected in series for driving an output load through output terminal 40, first control circuit 20 having invertors I1 and I2 and NOR gate N1 for controlling transistor FET1 of driving circuit 30, and second control circuit 10 having NAND gate N2 and invertor I3 for controlling FET2 of driving circuit 30.
Data D is applied through invertor I4 to an input of both NOR gate N1 and NAND gate N2, and control signal C is applied to invertor I1 and another input of NAND gate N2.
The conventional 3-state buffer circuit is operated in such a manner that, when 3-state control signal C is at a "low" level, the output of first control circuit 20 becomes a "high" level and the output of second control circuit 10 becomes a "low" level, whereby output transistors FET1 and FET2 are respectively controlled to be in the OFF state. In this state, output terminal 40 remains in a high impedance state by the low level of control signal C regardless of the state of data D.
On the other hand, when 3-state buffer control signal C is at a "high" level, since the output of invertor I1 becomes a "low" level, NOR gate N1 and NAND gate N2 are both put in an enabled state, and output terminal 40 follows input data D; that is, output terminal 40 becomes a "high" level if input data D is at a "high" level, and output terminal 40 becomes a "low" level if input data D is at a "low" level.
In this conventional 3-state buffer circuit, generally transistors FET1 and FET2 of driving circuit 30 must have a large current driving ability for driving quickly a capacitor CL of the output load connected to output terminal 40.
Particularly, in a chip having many output terminals 40, large sink current typically flows to the ground line. As a result, a large counter-electromotive force Vn is induced as shown in FIG. 2, which can act to pull up the voltage of the ground line, whereby an output delaying effect can occur as shown in FIG. 3. Here, inductance L causing the counter-electromotive force is the sum of inductances such as the inductances of the connecting lines and lead frame and the like within the chip, and this inductance L generally is unavoidable in the semiconductor chip. The resulting counter-electromotive force effectively becomes a source of ground noise.
In order to reduce such ground noise, one conventional 3-state buffer circuit operation method is that invertor I3 is designed to have decreased current driving ability, thereby turning on slowly output transistor FET2. Thus, the di/dt value is decreased.
Another operation method for a 3-state buffer circuit is to divide transistor FET2 so that multiple transistors are provided instead of single transistor FET2, with each transistor turning on in sequence with a time delay, thereby reducing the di/dt value.
However, it remains difficult to reduce the counter-electromotive force and to lessen the transfer time of the data from the input side to the output terminal.